This invention relates generally to III-V semiconductors and, more specifically, relates to contacts and MOSFETs formed on III-V semiconductors.
Self-aligned integration of III-V metal-oxide-semiconductor field effect transistor (MOSFET) is either challenging or complicated. In typical silicon-based semiconductor processing, there is a self-aligned silicide process, which is a process of forming a surface layer of metal silicide on a silicon substrate. Additionally, in III-V processing, there is a similar process (called germinide) to achieve self-aligned integration. Typically, germinide involves the selective growth of germanium at III-V source/drain regions, followed by subsequent formation of Ni—Ge alloys for contacts. Nevertheless, the challenges of this process include the high resistance of grown germanium layers and the high contact resistance between Ni—Ge alloy and the grown germanium.
Thus, there are few options in current III-V semiconductor processing for forming contacts on III-V semiconductors.